The present invention relates to a microprocessor including circuitry primarily useful for inserting a bus cycle to output an internal information for an emulation. The invention is particularly applicable to an execution instruction informing system for a microprocessor of the instruction prefetch type.
Some of the microcomputers proposed in the prior art have an instruction register of a prefetch type, in which some instructions are prefetched in addition to an instruction to be executed. Execution of a program can be speeded up by fetching a plurality of instructions in advance into the instruction register.
A user who has newly developed a microcomputer system or a software therefor frequently emulates for debugging. In this emulation, the execution of the program is interrupted at an instant when a certain instruction in the program is executed, or data on a bus is traced in the memory at a certain instant. By analyzing the content of the memory thus traced, the causes for a runaway of the program are clarified to facilitate the debugging of the program or system. A data bus or address bus is monitored during the emulation to detect a break point or trace point.
In a microcomputer having an instruction register for prefetching a plurality of instructions, as has been described above, the instruction code or address appearing on the actual bus is different from that of the instruction being executed, in case of the emulation. This makes it impossible to interrupt the execution of the program at a desired instant and makes it difficult to analyze the trace content after the emulation.
One proposal for overcoming this problem is disclosed in Japanese Patent Laid-Open No. 62-197831, in which an instruction being executed by a microcomputer of instruction prefetch type can be accessed from the outside by providing a pin for outputting the difference between the address of the instruction being executed and a prefetched address; or as disclosed in Japanese Patent Laid-Open No. 61-286936 in which an instruction execution occurs by making use of an interrupting function thereby to execute another instruction series for informing the internal state of the microprocessor to the outside.
Of the aforementioned prior art technologies, the system of providing a pin for outputting the difference between the address of the instruction being executed and the prefetched address is defective in that the production cost is raised, in that the period for development is elongated, and in that the system cannot cover the increase in the amount of information required, because the number of pins of the microprocessor has to be increased or because another chip has to be prepared with an additional special pin. On the other hand, the system in which the program is interrupted for each execution of instruction may lose its real time property or may runaway during the emulation.